The present invention relates generally to high voltage surface PN junctions and more specifically to an improved PN junction in a high doping surface.
Generally in semiconductor devices, a higher impurity concentration region is formed in the surface of a second region of opposite conductivity type and lower impurity concentration to form a PN junction. The surface of the substrate is usually covered with an insulative and protective layer. When these junctions are reverse biased, a depletion region is formed extending substantially into the lighter doped region. An electric field exists across the depletion region with its intensity higher in the vicinity of the surface. This results in a lower breakdown voltage for this region and thereby reduces the overall breakdown voltage of the PN junction.
In an effort to increase the breakdown voltage of the PN junction, it has been suggested in U.S. Pat. No. 3,463,977 to Grove et al. to provide field plates extending from the high impurity concentration region out across the low impurity concentration region along the surface. The field plates create an inverted region below the field plates which in itself will also reduce the breakdown characteristics of the junction if the reverse bias is large enough. To minimize this, Grove suggests increasing the thickness of the insulative layer below the field plate such that the breakdown voltage of the inverted region is not exceeded by the reverse biasing of of the PN junction. Grove also recognizes that the depletion layer thickness of the field induced junction increases with decreasing surface concentration. Thus, he recommends keeping the surface concentration as low as possible.
In high voltage applications including field plates, the thickness of the oxide must be carefully designed. As described in U.S. Pat. No. 3,767,981 to Polata, for a field plate to be effective, the insulation layer must be relatively thin while structures having high breakdown voltage require a relatively thick oxide layer between any charge carrying conductor in the substrate. Polata describes a tapered oxide layer extending from the junction outward as an optimization of both these requirements. Table 1 of Polata illustrates the relationship between the impurity concentration, critical electric field at which avalanche breakdown occurs, the magnitude of the electric field change from the surface, the maximum depletion layer and the maximum voltage that a one-sided junction can support. As can be seen with the increase of impurity concentration, the critical field increases, the rate of change of electrical field increases, maximum depth of the depletion region decreases and the maximum voltage at the junction can support decreases.
FIG. 2 illustrates a device similar to the one disclosed in Grove et al. It is a P+ N- diode having an N- region 20 with a P+ region 22 in its surface. An insulative protective layer 24 is formed on the surface and a field plate 26 is provided. When the PN junction 20, 22 is reverse biased, a depletion region 28 is formed extending from the PN junction 30. Electric field lines 32 are shown within the depletion region 28. As can be seen, the field plate 26 substantially modifies the horizontal component and spreads the vertical component of the electric field along the surface away from the surface portion of the PN junction 30.
The general variation of the vertical component of the electric field extending from the depleted portion 28 of the N- region 20 through the insulator 24 to the field plate 26 is shown in FIG. 3. The region where the electric field is highest is in the substrate at its surface and decreases monotonically away from the surface.
In some applications, it is very desirable to form a relatively high impurity concentration region in the surface of the semiconductor substrate having the same conductivity type as the substrate. Such a device is illustrated in FIG. 1 wherein the N region 34 has a higher impurity concentration than the N-substrate 20 in which the P region 22 is formed. As illustrated by the depletion region 28 and electric field lines 32, he electric field lines 32 are increased where the N region 34 abuts the curved portion of P region 22. This reduces the breakdown voltage for the junction 30 at the surface. To maintain high voltage junctions, the prior art spaced the N+ region 34 from the P region 22. This required additional steps to produce this separation.
Thus, it is an object of the present invention to maintain a high sustained reverse breakdown voltage while allowing the formation of a non-selective, high impurity concentration region on the low impurity side of a PN junction.
Another object of the present invention is to provide an improved lateral high voltage insulated gate field effect transistor device.
Yet another object of the present invention is to provide an improved double diffused lateral high voltage insulated gate field effect transistor.
Still another object of the present invention is to provide a high voltage lateral bipolar transistor having a punch-through shield.
A further object of the present invention is to provide a high voltage, low collector resistance, vertical bipolar transistor.
An even further object of the present invention is to provide a high CEO bipolar transistor and a high impurity concentration surface region.
These and other objects of the invention are attained by providing a field plate separated from the surface of the lighter doped side of a PN junction and a higher impurity concentration region at the surface of the lighter doped side of the same conductivity type and extending down along a substantial portion of the higher doped side of the PN junction. The impurity concentration of the lighter doped side of the PN junction including its higher impurity concentration surface region is selected so that the surface region is depleted by biasing the field plate before critical field is reached therein. The PN junction may be the body-drain junction of the double diffused lateral MOS transistor, the junction of the source and drain regions with the body of a lateral insulator field effect transistor, the collector-base junction of a lateral bipolar transistor, or the base-collector junction of a vertical bipolar transistor.